Circuit for reducing pulse pile-up in pulse detection systems

ABSTRACT

The amplified pulses from a radioactivity detector are coupled to a discriminator and via a 400 nanosecond delay line to the inputs of three linear gates. The discriminator is AND gated with a clock pulse and a J-K flip-flop. A scale of four and a 1 of 4 decoder and a single shot multivibrator are driven by the AND gate output. The single shot output and the decoder outputs are AND gated to control the linear gates. In an alternative embodiment, the linear gates and delay lines are replaced with charge and hold, delay and interrogate circuits.

United States Patent Culver CIRCUIT FOR REDUCING PULSE PILE-UP IN PULSEDETECTION SYSTEMS Primary Examiner-James W. Lawrence AssistantExaminer-D. C. Nelms Attorney-Robert W. Mayer, Thomas P. Hubbard, Jr.,

[75 1 Dil te)? llllyf k iflffjfi Daniel Rubin, Raymond T. Majeako, Roy1.. Van Win- [73] Assignee: Dresser Industries, Inc.,Dallas, TeX.William JOhIl-SOD, J11, Eddie sco and L. 22 Filed: June 1, 1971 Cmw 21Appl. No.: 148,765 57] ABSTRACT The amplified pulses from aradioactivity detector are [52] 0.5. Cl.........................II...I[26/270,250/363 P a discriminamr and via 8511 1111.01. 11013 39/30 delay line to the inputs of three 8 [58] Fieldof Search 250/83.6 w, 83.3 R; criminator is AND sated with a clock pulseand a 307/232, 234, 260; 328/59, 10 flip-flop. A scale of four and a lof 4 decoder and a single shot multivibrator are driven by the AND gateout- 56] References cued put. The single shot output and the decoderoutputs are UNITED STATES PATENTS AND gated to control the linear gates.3 309 521 3/1967 Bargainer 250/336 w an a'wmaive embcdimen" linear gateand 3/1969 Zcmanek 250/836 w delay lines are replaced with charge andhold, delay 3,559,163 1/1971 Schwartz.... 250/83.6 w and inmroaatecircuits 3,275,826 9/l966 Leiter 250/833 R 2 Drawing l 23 1 T 11 1 2 24Q DISCRIMINATOR K K QEEE'I if? 25 27 CLOCK 1s 5 NEUTRON 7/ 3B 1111/SOURCE L1 SCALER SINGLE SHOT L DELAY MULTIVIBRATOR 26 016112;, 3 T 0 l12 3 g 32 1.1M: 20 AMPLIFIER .us 34 as 3 36 are 51:; 222

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A TTORNE Y CIRCUIT FOR REDUCING PULSE PILE-UP IN PULSE DETECTION SYSTEMSRELATED APPLICATIONS This application relates to my co-pendingapplication, Ser. No. 146,261, filed May 24, l97l, entitled CIRCUIT FORIMPROVING DATA IN PULSE DE TECTION SYSTEMS, and to my concurrently filedcopending application Ser. No. 148,754, filed June 1, 1971, entitledCIRCUIT FOR REDUCING PULSE PILE-UP IN PULSE DETECTION SYSTEMS BYCONVERTING A RANDOM PULSE TRAIN TO THAT F FIXED FREQUENCY.

BACKGROUND OF THE INVENTION This invention relates generally to the artof geophysical prospecting and more particularly to the art ofradioactivity well logging involving the counting of pulses resultingfrom the detection of such radioactivity.

As is well known in the art of radioactivity well logging, the detectionof gamma rays from the inelastic scattering of fast neutrons isgenerally accomplished by pulsing a scintillation detectorcoincidentally with a fast neutron source. The difficulties involved inthis measurement are numerous, notthe least being the slow rate ofaccumulating data.

Sodium iodide detectors are normally used in subsurface spectralmeasurement systems because they offer the best compromise of physicaland electrical characteristics. Good linearity and resolution can beobtained with detector output pulse widths of about 1.2 microseconds.However, when the pulses are transmitted over a well logging cable, anypulse arriving at the surface for analysis will have been spread in timeto about microseconds by its transit over the 4 miles of cable thattypically separates the surface and subsurface sys terns.

The fast multichannel analyzers that are presently available have pulsepair resolving times of about microseconds for pulses of this width. Themaximum pulse rate will be less than the detector pulsing frequency ifgood resolution is maintained. This is due to the statistical nature ofthe data; as the average data rate approaches the pulsing frequency, theprobability of a second detector pulse occurring during the detectorgating interval becomes large, and the pulse spectrum is distorted dueto pulse pile-up on the line.

It is therefore the primary object of the present invention to provide acircuit which substantially reduces the problem of pulse pile-up on theline; and

It is another object of the invention to provide a new and improvedcircuit for preventing pulse pile-up on the line by delaying theprocessing of any pulses that would otherwise follow too soon after anygiven pulse.

SUMMARY OF THE INVENTION The objects of the invention are accomplished,broadly, by a circuit which utilizes a combination of energydiscrimination and delay logic for eliminating pulse pile-up bydelayingthe processing of any pulses that would otherwise follow toosoon after any given pulse.

These and other objects, features and advantages of the invention willbecome apparent to those skilled in the art from the following detaileddescription, when considered with the accompanying drawing, in which:

FIG. 1 is a block circuit diagram of one embodiment of the invention;and

FIG. 2 is a block circuit diagram of an alternative embodiment of theinvention.

Referring to the drawing in more detail, particularly to FIG. I, thereis illustrated in block diagram a circuit which can be used to aid inreducing the probability of pulse pile-up within instrumentation whichis used in conducting a radio-activity well survey. It should beappreciated that the circuits embodied herein find utility in myabove-referenced co-pending applications and the disclosure of suchapplications is incorporated herein by reference. I

The detector 10, which may be used in a well logging instrument notillustrated, is a scintillation counter arranged for gamma ray spectralanalysis in accordance with prior art. In the preferred embodiment, itis a NaI (Tl) crystal having a 2 inch diameter with a 3 inch length,such crystal being coupled to a Model No. 4518 photomultiplier tubeavailable from the Radio Corporation of America. Such acrystal-photomultiplier combination may have a resolution of 7.5 to 8.5percent with a 660 kev cesium 137 peak. The output of the detector 10 iscoupled into a discriminator 11, which in turn is coupled into one ofthe three inputs to the AND gate 12. The discriminator 11 is used toremove pulses having amplitude below a selectable threshold value whichmight otherwise cause pile-up on the transmission line normallyconnected to the output terminal 33. A setting of 400 kev is generallysuitable for this purpose. The output of the discriminator 11 is ANDgated in the AND gate 12 with a voltage pulse having a nominal width often microseconds from the clock and sequence circuit 13. The output ofthe AND gate 12 triggers a single shot multivibrator circuit 14. Theclock 13 is also synchronized with the neutron source 15. The pulse fromthe clock actuates a high voltage pulser (not illustrated) arranged tocause the neutron output of neutron source 15 to pulse at the clockfrequency as described in US. Pat. No. 3,309,522.

The amplified pulses from the detector I0 are also coupled into thedelay line 16, which is nominally set to cause a delay of .4microseconds, the output of which is coupled into the three lineargates", 18 and 19. H j I The output of the single shot multivibrator 14is coupled into the first gate on each of three AND gates 20, 21 and 22,respectively, the outputs of which are coupled into the linear gates 17,18 and I9,respectively.

As previously mentioned, two of the inputs to the AND gate 12 areconnected to the output of the clock 13 and the discriminator ll,respectivelyfThe third gate of the AND gate 12 is connected to the 6output of the J-K flip-flop circuit 23. Such .JK flip-flop circuits areconventional and are discussed at length in US Pat. No. 3,268,741. Thesteering terminal K is also connected to the 6 output terminal. Theoutput of the clock 13 is also connected to the clear input terminal 24of the circuit 23. The clock pulse input terminal 25 of the .I-Kflip-flop circuit 23 (not to be confused with the clock 13) is connectedto the output of an inverter which is driven by the decoder output 3 ofthe de- The output of the AND gate 12 is connected to the scaler circuit28. Such scaler circuits are conventional, and can be a pair offlip-flop multivibrators cascaded to provide a scale of four operationif desired. The four outputs of the scaler circuit 28 are connected intoa l of 4 decoder 26 for decoding the scaler circuit. The output isunconnected on the decoder 26. The 1", 2 and 3 outputs of the decoder 26are connected to the second inputs of the AND-gates 20, 21 and 22,respectively.

The output of linear gate 17 is connected to a pulse shaping circuit 30and a resistor 31 and further into the line amplifier 32 and the outputterminal 33. The output terminal 33 corresponds to a point which wouldnormally be associated with the amplification and transmittal of pulsesto the earths surface in well logging utility.

The output of the linear gate 18 is connected through a delay line 34 tothe pulse shaper circuit 35 and through the resistor 36 to the lineamplifier 32. In a similar manner, the output of linear gate 19 isconnected through the delay line 37 and the pulse shaper circuit 38 andthrough the resistor 39 to the line amplifier 32.

In the operation of the circuit of FIG. 1, it should be understood thatthe delay line 16 allows for thetime required for the detector pulses torise to the trigger level of the discriminator and for propagation timesin the logic circuits. The clock pulse from the clock 13 enables the J-Kflip-flop (an End Sequence circuit) in its high output state, and thefirst detector pulse above the discriminator threshold and within thegating interval from the clock produces an output from the AND gate 12which triggers the single shot multivibrator l4 and also advances thescale of four decoder to position 1. Such action enables the AND gateand thus the linear gate 17. The output of the linear gate 17 is passedthrough the pulse shaper circuit 30 to the line amplifier 32 foramplification and transmission to the earths surface. The seconddetector pulse falling within the clock interval exceeding thediscriminator threshold produces an output from the single shot andadvances the sealer-decoder to position 2. The AND gate 21 and lineargate 18 are thus enabled and the detector pulse passes through thelinear gate 18 and is delayed by delay line 34 before being shaped bythe pulse shaper circuit 35 and being passed to the line amplifier 32.The third detector pulse falling within the clock interval which exceedsthe discriminator threshold triggers the single shot multivibrator againand advances the decoder to position 3. The AND gate 22 and linear gate19 are thus enabled and the detector pulse passes therethrough to bedelayed by delay line 37 and shaped by the pulse shaper circuit 38 andamplified by the line amplifier 32. Also the inverted decoder output 3"causes the J-K flip-flop circuit to change state and disable theAND'gate 12. The scale of four circuit 28 is reset to zero by the outputof the reset generator 27 which occurs at some convenient time beforethe next clock pulse. It should be appreciated that even if less thanthree pulses occur during the clock interval, the AND gate 12 isdisabled by the clock pulse going to zero.

For all of the pulses to be analyzed as individual pulses, it isdesirable that the delay of delay lines 34 and 37 be slightly longerthan the longest dead time in the system. This may be the line dead timeor the pulse pair resolving time of the surface equipment (notillustrated). The shaper circuits are included to compensate forperturbations caused by the delay lines. The system is adjustedinitially by feeding a standard pulse to the input, coinciding with theoutput of the detector 10, and adjusting the shaper circuits so that thepulse falls in the same channel of the surface analyzing equipmentregardless of the channel it passes through in the subsurface system.

Delay lines of long delay, for example 10 to I00 microseconds, arephysically large if good pulse fidelity is to be maintained; therefore,an alternate means for accomplishing the delay is shown in FIG. 2hereinafter.

Referring now to FIG. 2, the charge and hold circuits 40, 41 and 42replace the linear gates l7, l8 and 19 as illustrated with respect toFIG. 1, respectively. The charge and hold circuits 40, 41 and 42 areconnected to the outputs of the AND gates 20, 21 and 22, respectively.The output of the AND gate 20 is also connected to a delay circuit 43which may be a delay line or a single shot multivibrator which in turnis connected to a gate 44, for example, a single shot multivibrator,which is used to gate an interrogator circuit 45. A capacitor C1 isassociated with the charge and hold circuit 40 for the storage of anydetector pulse appearing in the circuit 40. The interrogator circuit 45,for example a linear gate circuit, also has means for discharging thecapacitor C1 in a manner known in the art since such interrogatorcircuits are conventional. The output of the interrogator circuit 45 iscoupled through a resistor 46 to the line amplifier 32.

In a similar manner, the output of the AND gate 21 is connected througha similar delay and gate circuit into the interrogator 47. Likewise, theoutput of AND gate 22 is connected to a delay circuit and a gate circuitinto the interrogator circuit 48. The output of interrogator circuit 47is connected through a variable resistor 49 to the line amplifier 32.The output of interrogator circuit 48 is similarly connected through avariable resistor 50 to the line amplifier 32.

In the operation of FIG. 2, it should be appreciated that its operationis very similar to that of FIG. 1. The clock pulse enables the J-Kflip-flop in its high output state and the first detector pulseappearing within the clock interval and above the discriminatorthreshold produces an output from the single shot multivibrator l4 andalso advances the decoder circuit 26 to position l. The charge and holdcircuit 40 is activated and the capacitor C1 is charged to the peakvalue of the detector pulse. Also, delay circuit 43, for example asingle shot multivibrator, is triggered which in turn triggers the gatecircuit 44 which in turn activates the interrogator 45 and the resultingoutput is coupled to the line amplifier 32. The second detector pulsefalling within the clock interval and exceeding the discriminatorthreshold produces an output from the single shot multivibrator 14 andadvances the decoder to position 2." The charge and hold circuit 41 isactivated and the capacitor C2 is charged to the peak value of thedetector pulse. Also the delay circuit associated with the AND gate 21and its associated gate is triggered which activates the interrogator 47and the resulting output is fed to the line amplifier 32. The thirddetector pulse is processed by the interrogator 48 in a similar manner.The decoder output 3 causes the .l-K flip-flop to change state anddisable the AND gate 12.

The delay of the delay circuit 43 can be short, but the delay of thedelay circuits associated with the outputs of the AND gates 21 and 22,respectively, should be slightly longer than the longest dead time inthe system.

If identical circuits are used in each channel, and if the interrogatoraperature width is the same for all channels, the output of theinterrogators will differ only by the amount of charge that leaks offthe hold capacitors C1, C2 and C3 due to circuit imperfections.Compensation for this is made by adjusting the value of the lineamplifier input resistor for each channel, such as by adjusting theresistors 49 and 50. The initial adjustment is made by feeding astandard pulse to all channels, adjusting the resistor in each channelso that all pulses are resolved the same by the surface equipment. Withcarefully designed circuits, long delays and accurate reproduction ofthe detector pulses result.

For ease of illustration, the circuits in FIG.s l and 2 have beendescribed for processing a maximum of three detector pulses per gatinginterval. It should be appreciated, however, that more or less pulsescan be processed by a different number of channels. The length of thegating interval and the decay time of the detector will determine themaximum. This method has been shown to greatly increase the data ratewhen fast detectors are used, such as with solid state. or other fastdetectors.

It it is desirable to process all detector pulses, the discriminator isset just above the noise level. However, additional pulse selection canbe made by adjusting the threshold to eliminate undesirable low energypulses.

I claim:

1. In a radioactivity well logging system having a pulsed neutron sourceand a radioactivity detector wherein electrical pulses tend to pile upwithin the system, the improvement comprising means to selectively gateand transmit to the earth's surface a first electrical pulse indicativeof detected radiation following the commencement of each neutron sourcepulse and to gate a second such electrical pulse and to transmit saidsecond electrical pulse to the earth's surface only after apredetermined delay following the transmission of said first electricalpulse.

2. In the system according to claim I, said selective gating means beingfurther characterized as being synchronized with the pulsing of saidneutron source.

3. In the system according to claim 2, said selective gating means beingfurther characterized as including means to discriminately gate onlythose pulses having a predetermined characteristic.

4. In the system according to claim 3, wherein said predeterminedcharacteristic is functionally related to the energy level of gamma raysof interest emanating from the formations surrounding the well bore.

5. In a radioactivity well logging system having a pulsed neutron sourceand a radioactivity detector wherein electrical pulses tend to pile upwithin the system, the improvement comprising means to selectively gatea plurality of electrical pulses indicative of detected radiationfollowing the commencement of each neutron source pulse, said meansincluding delay means for introducing predetermined delays between saidelectrical pulses prior to their transmission to the earth's surface.

6. In the system according to claim 5, said selective gating means beingfurther characterized as being synchronized with the pulsing of saidneutron source.

7. In the system according to claim 6, said selective gating means beingfurther characterized as including means to discriminately gate onlythose pulses having a predetermined characteristic.

8. In the system according to claim 7, wherein said predeterminedcharacteristic is functionally related to the energy level of gamma raysof interest emanating from the formations surrounding the well bore.

9. In an electrical circuit in which electrical pulses are cyclicallyassociated with a synchronized event, the improvement comprising:

clock means for producing a series of synchronizing gate pulses;

an input terminal for receiving electrical pulses associated with saidsynchronizing gate pulses;

delay means connected to said input terminal;

a first electrical AND gate having one of its three inputs connected tosaid input terminal;

a J-K flip-flop circuit having a first input steering terminal, aclearing input terminal and a clock input terminal and providing anoutput signal at an output terminal of said flip-flop circuit, saidclearing input terminal being connected to said clock means and also tothe second input of said first AND gate and said input steering terminalof said 144 flip-flop circuit being connected to the output terminal ofsaid flip-flop circuit and to the third input of said first AND gate;

a plurality of additional AND gates having two inputs each;

a single shot multivibrator connected to, and driven by, the output ofsaid first AND gate, the output of said multivibrator being connected tothe first input of each of said additional gates for triggering saidgates;

a sealer-decoder connected to the output of said multivibrator, theoutputs of said decoder being connected to the second inputs of saidadditional gates, respectively, the last used decoder output beingconnected to said clock input terminal of said .I-K flip-flop circuit;

a plurality of linear gates, each of which is connected to the output ofsaid delay means, and such linear gates being connected to be triggeredby the outputs of the plurality of additional AND gates, respectively;and

an output terminal connected to the outputs of said linear gates.

10. The circuit according to claim 9, including in addition thereto, areset generator for resetting said sealer-decoder in synchronizationwith said clock pulses.

11. The circuit according to claim 10, including in addition thereto,additional delay means connected to the outputs of at least one of saidlinear gates.

12. In an electrical circuit in which electrical pulses are cyclicallyassociated with a synchronized event, the improvement comprising:

clock means for producing a series of synchronizing gate pulses;

an input terminal for receiving electrical pulses associated with saidsynchronizing gate pulses;

delay means connected to said input terminal;

a first electrical AND gate having one of its three inputs connected tosaid input terminal;

a J-K flip-flop circuit having a first input steering terminal, aclearing input terminal and a clock input terminal and providing anoutput signal at an out put terminal of said flip-flop circuit, saidclearing input terminal being connected to said clock means and also tothe second input of. said first AND gate and said input steeringterminal of said J-K flip-flop circuit being connected to the outputterminal of said flip-flop circuit and to the third input of said firstAND gate;

a plurality of additional AND gates having two inputs each;

by, the output of said first AND gate, the output of said multivibratorbeing connected to the first input of each of said additional gates fortriggering said gates;

a sealer-decoder connected to the output of said multivibrator, theoutputs of said decoder being connected to the second inputs of saidadditional gates, respectively, the last used decoder output beingconnected to said clock input terminal of said .l-K flip-flop circuit;

a plurality of charge and hold circuits, each of which single shotmultivibrator connected to, and driven 10 is connected to the output ofsaid delay means, and such charge and hold circuits being connected tobe triggered by the outputs of the plurality of additional AND gates,respectively;

means to interrogate said charge and hold circuits;

and

an output terminal connected to said interrogator means.

13. The circuit according to claim 12 wherein said interrogator meansincludes a separate interrogator circuit for each of said plurality ofcharge and hold circuits.

14. The circuit according to claim 13, including in addition thereto,means to gate said separate interrogator circuits connected to theoutputs of said additional AND gates.

15. The circuit according to claim 14, including in addition thereto,discriminator means between said input terminal and said first AND gate.

1. In a radioactivity well logging system having a pulsed neutron sourceand a radioactivity detector wherein electrical pulses tend to pile upwithin the system, the improvement comprising means to selectively gateand transmit to the earth''s surface a first electrical pulse indicativeof detected radiation following the commencement of each neutron sourcepulse and to gate a second such electrical pulse and to transmit saidsecond electrical pulse to the earth''s surface only after apredetermined delay following the transmission of said first electricalpulse.
 2. In the system according to claim 1, said selective gatingmeans being further characterized as being synchronized with the pulsingof said neutron source.
 3. In the system according to claim 2, saidselective gating means being further characterized as including means todiscriminately gate only those pulses having a predeterminedcharacteristic.
 4. In the system according to claim 3, wherein saidpredetermined characteristic is functionally related to the energy levelof gamma rays of interest emanating from the formations surrounding thewell bore.
 5. In a radioactivity well logging system having a pulsedneutron source and a radioactivity detector wherein electrical pulsestend to pile up within the system, the improvement comprising means toselectively gate a plurality of electrical pulses indicative of detectedradiation following the commencement of each neutron source pulse, saidmeans including delay means for introducing predetermined delays betweensaid electrical pulses prior to their transmission to the earth''ssurface.
 6. In the system according to claim 5, said selective gatingmeans being further characterized as being synchronized with the pulsingof said neutron source.
 7. In the system according to claim 6, saidselective gating means being further characterized as including means todiscriminately gate only those pulses having a predeterminedcharacteristic.
 8. In the system according to claim 7, wherein saidpredetermined characteristic is functionally related to the energy levelof gamma rays of interest emanating from the formations surrounding thewell bore.
 9. In an electrical circuit in which electrical pulses arecyclically associated with a synchronized event, the improvementcomprising: clock means for producing a series of synchronizing gatepulses; an input terminal for receiving electrical pulses associatedwith said synchronizing gate pulses; delay means connected to said inputterminal; a first electrical AND gate having one of its three inputsconnected to said input terminal; a J-K flip-flop circuit having a firstinput steering terminal, a clearing input terminal and a clock inputterminal and providing an output signal at an output terminal of saidflip-flop circuit, said clearing input terminal being connected to saidclock means and also to the second input of said first AND gate and saidinput steering terminal of said J-K flip-flop circuit being connected tothe output terminal of said flip-flop circuit and to the third input ofsaid first AND gate; a plurality of additional AND gates having twoInputs each; a single shot multivibrator connected to, and driven by,the output of said first AND gate, the output of said multivibratorbeing connected to the first input of each of said additional gates fortriggering said gates; a scaler-decoder connected to the output of saidmultivibrator, the outputs of said decoder being connected to the secondinputs of said additional gates, respectively, the last used decoderoutput being connected to said clock input terminal of said J-Kflip-flop circuit; a plurality of linear gates, each of which isconnected to the output of said delay means, and such linear gates beingconnected to be triggered by the outputs of the plurality of additionalAND gates, respectively; and an output terminal connected to the outputsof said linear gates.
 10. The circuit according to claim 9, including inaddition thereto, a reset generator for resetting said scaler-decoder insynchronization with said clock pulses.
 11. The circuit according toclaim 10, including in addition thereto, additional delay meansconnected to the outputs of at least one of said linear gates.
 12. In anelectrical circuit in which electrical pulses are cyclically associatedwith a synchronized event, the improvement comprising: clock means forproducing a series of synchronizing gate pulses; an input terminal forreceiving electrical pulses associated with said synchronizing gatepulses; delay means connected to said input terminal; a first electricalAND gate having one of its three inputs connected to said inputterminal; a J-K flip-flop circuit having a first input steeringterminal, a clearing input terminal and a clock input terminal andproviding an output signal at an output terminal of said flip-flopcircuit, said clearing input terminal being connected to said clockmeans and also to the second input of said first AND gate and said inputsteering terminal of said J-K flip-flop circuit being connected to theoutput terminal of said flip-flop circuit and to the third input of saidfirst AND gate; a plurality of additional AND gates having two inputseach; a single shot multivibrator connected to, and driven by, theoutput of said first AND gate, the output of said multivibrator beingconnected to the first input of each of said additional gates fortriggering said gates; a scaler-decoder connected to the output of saidmultivibrator, the outputs of said decoder being connected to the secondinputs of said additional gates, respectively, the last used decoderoutput being connected to said clock input terminal of said J-Kflip-flop circuit; a plurality of charge and hold circuits, each ofwhich is connected to the output of said delay means, and such chargeand hold circuits being connected to be triggered by the outputs of theplurality of additional AND gates, respectively; means to interrogatesaid charge and hold circuits; and an output terminal connected to saidinterrogator means.
 13. The circuit according to claim 12 wherein saidinterrogator means includes a separate interrogator circuit for each ofsaid plurality of charge and hold circuits.
 14. The circuit according toclaim 13, including in addition thereto, means to gate said separateinterrogator circuits connected to the outputs of said additional ANDgates.
 15. The circuit according to claim 14, including in additionthereto, discriminator means between said input terminal and said firstAND gate.